Mechanical stresses within a semiconductor device substrate have been widely used to modulate device performance. For example, in common Si technology, the channel of a transistor is oriented along the {110} planes of silicon. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the primary direction of charge transport and/or under tensile stress in a direction normal of the channel, while the electron mobility is enhanced when the silicon film is under tensile stress in the primary direction of charge transport and/or under compressive stress in the direction normal to the primary direction of charge transport of the channel. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-channel field effect transistor (pFET) and/or an n-channel field effect transistor (nFET) to enhance the performance of such devices.
One possible approach for creating a desirable stressed silicon channel region is to form embedded Si:C or SiGe stressors (i.e., stress wells) at the source and drain regions of a CMOS device to induce compressive or tensile strain in the channel region located between the source and drain regions. Although embedded stressor technology is now well-known, the integration of the embedded stressor into the normal CMOS process flow is extremely challenging. The extent of the performance of the CMOS device depends strongly on the stress generated by the embedded stressor itself, the active dopant concentration in the embedded stressor and the proximity of the embedded stressor to the device channel region.
Despite these advances in the semiconductor industry, further improvement in embedded stressor technology is needed that provides a good balance between stressor proximity and short channels effects. A disadvantage of the stressors of the related art is that they are located relatively far away from the channel. Moreover, an embedded stressor technology is needed that also eliminates possible defect generation, which typically occurs during the ion implantation of deep source/drain regions in embedded stressor technology of the related art. However, this approach does not maximize the extent of performance gain that can be achieved.